An active matrix-type display device displays an image by selecting two-dimensionally arranged pixel circuits on a row-by-row basis and writing grayscale voltages according to a video signal to the selected pixel circuits. Such a display device is provided with a scanning signal line drive circuit including a shift register, to select pixel circuits on a row-by-row basis.
For a method of making a display device small, there is known a method in which a scanning signal line drive circuit is integrally formed with pixel circuits on a display panel, using a fabrication process for forming TFTs (Thin Film Transistors) in the pixel circuits. The scanning signal line drive circuit is formed using, for example, amorphous silicon TFTs. A display panel having an integrally formed scanning signal line drive circuit is also called a gate driver monolithic panel.
For a shift register included in a scanning signal line drive circuit, various types of circuits are conventionally known (e.g., Patent Documents 1 to 3). Patent Document 1 describes a shift register in which unit circuits 91 shown in FIG. 15 are connected in multi-stage. Each unit circuit 91 includes five transistors Q1 to Q5 and a capacitor C1. The transistor Q2 functions as an output transistor that changes an output signal OUT from the shift register to a predetermined level (here, high level). Patent Documents 2 and 3 also describe shift registers in which unit circuits, each including an output transistor, are connected in multi-stage.
FIG. 16 is a diagram showing a connection configuration of an output transistor. As shown in FIG. 16, a clock signal CK is provided to the drain terminal of an output transistor Qo, the gate terminal is connected to a node N1, and the source terminal is connected to an output terminal OUT. In this circuit, a parasitic capacitance Cp occurs between the gate and drain of the output transistor Qo. Hence, when the clock signal CK changes, the potential at the node N1 also changes through the parasitic capacitance Cp. In particular, when the clock signal CK changes to high level while the potential at the node N1 is at low level, the potential at the node N1 becomes higher than a normal low-level potential. Hence, leakage current of the output transistor Qo increases and thus the low-level potential of an output signal OUT becomes unstable.
To solve this problem, the unit circuit 91 includes the transistor Q5. In the unit circuit 91, when the clock signal CK goes to high level, the transistor Q5 is placed in on state and a low-level potential of the output signal OUT is applied to the node N1. By thus repeatedly applying a low-level potential to the node N1, the low-level potential of the output signal OUT can be stabilized.